Improving Software Pipelining by Hiding Memory Latency

Modern processors and compilers hide long memory latencies through non-blocking loads or explicit software prefetching instructions. Unfortunately , each mechanism has potential drawbacks. Non-blocking loads can signiicantly increase register pressure by extending the lifetimes of loads. Software prefetching increases the number of memory instructions in the loop body. For a loop whose execution time is bound by the number of loads/stores that can be issued per cycle, software 1 2 prefetching exacerbates this problem and increases the number of idle computational cycles in loops. In this paper, we show how compiler and architecture support for combining a load and a prefetch into one instruction, called a prefetch-ing load, can give lower register pressure like software prefetching and lower load/store-unit requirements like non-blocking loads. On a set of 106 Fortran loops we show that prefetching loads obtain a speedup of 1.07{1.53 over using just non-blocking loads and a speedup of 1.04{1.08 over using software prefetching. In addition, prefetching loads reduced oating-point register pressure by as much as a factor of 0.4 and integer register pressure by as much as a factor of 0.8 over non-blocking loads. Integer register pressure was also reduced by a factor of 0.97 over software prefetching, while oating-point register pressure was increased by a factor of 1.02 versus software prefetching in the worst case.